RSS订阅SMBUS
贡献者：gsfei2009 浏览：7514次 创建时间：2009-06-23
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The System Management Bus (abbreviated to SMBus or SMB) is a simple two-wire bus, derived from I?C and used for communication with low-bandwidth devices on a motherboard, especially power related chips such as a laptop's rechargeable battery subsystem (see Smart Battery Data). Other devices might include temperature, fan or voltage sensors, lid switches and clock chips. PCI add-in cards may connect to an SMBus segment.
A device can provide manufacturer information, indicate its model/part number, save its state for a suspend event, report different types of error, accept control parameters and return status. The SMBus is generally not user configurable or accessible. Although SMBus devices usually can't identify their functionality, a new PMBus coalition has extended SMBus to include conventions allowing that.
The SMBus was defined by Intel in 1995. It carries clock, data, and instructions and is based on Philips' I?C serial bus protocol. Its clock frequency range is 10 kHz to 100 kHz. (PMBus extends this to 400 kHz.) Its voltage levels and timings are more strictly defined than those of I?C, but devices belonging to the two systems are often successfully mixed on the same bus.
Contents [hide]
1 SMBus/I2C Interoperability
1.1 Electrical
1.1.1 Input Voltage (VIL and VIH)
1.1.2 Sink Current (IOL)
1.1.3 Frequency (FMAX and FMIN)
1.1.4 Timing
1.2 Protocols
1.2.1 ACK and NACK usage
1.2.2 SMBus protocols
1.2.3 Address Resolution Protocol
1.2.4 Time-out feature
1.2.5 Packet Error Checking
1.2.6 SMBALERT#
2 SMBus Support
3 See also
4 External links
5 References
[edit] SMBus/I2C Interoperability
While SMBus is derived from I2C, there are several major differences between the specifications of the two busses in the areas of electricals, timing, protocols and operating modes.[1][2][3]
[edit] Electrical
[edit] Input Voltage (VIL and VIH)
When mixing devices, the I2C specification defines the VDD to be 5.0 Volt +/- 10% and the fixed input levels to be 1.5 and 3.0 Volts. Instead of relating the bus input levels to VDD, SMBus defines them to be fixed at 0.8 and 2.1 Volts. This SMBus specification allows for bus implementations with VDD ranging from 3 to 5 Volts +/- 10%.
[edit] Sink Current (IOL)
SMBus has a ‘High Power’ version 2.0 that includes a 4 mA sink current that cannot be driven by I2C chips unless the pull-up resistor is sized to I2C-bus levels.
NXP devices have a higher power set of electrical characteristics than SMBus 1.0. The main difference is the current sink capability with VOL = 0.4 V.
SMBus low power = 350 μA
SMBus high power = 4 mA
I2C-bus = 3 mA
SMBus ‘high power’ devices and I2C-bus devices will work together if the pull-up resistor is sized for 3 mA.
[edit] Frequency (FMAX and FMIN)
The SMBus clock is defined from 10 kHz to 100 kHz while I2C can be 0 Hz to 100 kHz, 0 Hz to 400 kHz, 0 Hz to 1 MHz and 0 Hz to 3.4 MHz, depending on the mode. This means that an I2C-bus running at less than 10 kHz will not be SMBus compliant since the SMBus devices may time out. Many SMBus devices will however support lower frequencies.
[edit] Timing
SMBus defines a clock low time-out, TTIMEOUT of 35 ms. I2C does not specify any timeout limit.
SMBus specifies TLOW: SEXT as the cumulative clock low extend time for a slave device. I2C does not have a similar specification.
SMBus specifies TLOW: MEXT as the cumulative clock low extend time for a master device. Again I2C does not have a similar specification.
SMBus defines both rise and fall time of bus signals. I2C does not.
The SMBus time-out specifications do not preclude I2C devices co-operating reliably on the SMBus. It is the responsibility of the designer to ensure that I2C devices are not going to violate these bus timing parameters.
[edit] Protocols
[edit] ACK and NACK usage
There are the following differences in the use of the NACK bus signaling: In I2C, a slave receiver is allowed not to acknowledge the slave address, if for example is unable to receive because it’s performing some real time task. SMBus requires devices to acknowledge their own address always, as a mechanism to detect a removable device’s presence on the bus (battery, docking station, etc.) I2C specifies that a slave device, although it may acknowledge its own address, some time later in the transfer it may decide that it cannot receive any more data bytes. The I2C specifies, that the device may indicate this by generating the not acknowledge on the first byte to follow. Besides to indicate a slave device busy condition, SMBus is using the NACK mechanism also to indicate the reception of an invalid command or data. Since such a condition may occur on the last byte of the transfer, it is required that SMBus devices have the ability to generate the not acknowledge after the transfer of each byte and before the completion of the transaction. This is important because SMBus does not provide any other resend signaling. This difference in the use of the NACK signaling has implications on the specific implementation of the SMBus port, especially in devices that handle critical system data such as the SMBus host and the SBS components.
[edit] SMBus protocols
Each message transaction on SMBus follows the format of one of the defined SMBus protocols. The SMBus protocols are a subset of the data transfer formats defined in the I2C specifications. I2C devices that can be accessed through one of the SMBus protocols are compatible with the SMBus specifications. I2C devices that do not adhere to these protocols cannot be accessed by standard methods as defined in the SMBus and ACPI specifications.
[edit] Address Resolution Protocol
The SMBus uses I2C hardware and I2C hardware addressing, but adds second-level software for building special systems. In particular its specifications include an Address Resolution Protocol that can make dynamic address allocations. Dynamic reconfiguration of the hardware and software allow bus devices to be ‘hot-plugged’ and used immediately, without restarting the system. The devices are recognized automatically and assigned unique addresses. This advantage results in a plug-and-play user interface. In both those protocols there is a very useful distinction made between a System Host and all the other devices in the system that can have the names and functions of masters or slaves.
[edit] Time-out feature
SMBus has a time-out feature which resets devices if a communication takes too long. This explains the minimum clock frequency of 10 kHz to prevent locking up the bus. I2C can be a ‘DC’ bus, meaning that a slave device stretches the master clock when performing some routine while the master is accessing it. This will notify to the master that the slave is busy but does not want to lose the communication. The slave device will allow continuation after its task is complete. There is no limit in the I2C-bus protocol as to how long this delay can be, whereas for a SMBus system, it would be limited to 35 ms. SMBus protocol just assumes that if something takes too long, then it means that there is a problem on the bus and that all devices must reset in order to clear this mode. Slave devices are not then allowed to hold the clock LOW too long.
[edit] Packet Error Checking
SMBus 2.0 allows enabling Packet Error Checking (PEC). In that mode, a PEC (packet error code) byte is appended at the end of each transaction. The byte is calculated as CRC-8 checksum, calculated over the entire message including the adress and read/write bit. The polynomial used is x8+x2+x+1 (the CRC-8-ATM HEC algorithm, initialized to zero). [4] [5] [6]
[edit] SMBALERT#
The SMBus has an extra optional shared interrupt signal called SMBALERT#, which can be used by slaves to tell the host to ask its slaves about events of interest. SMBus also defines a less common "Host Notify Protocol", providing similar notifications but passing more data and building on the I?C multi-master mode.
[edit] SMBus Support
FreeBSD, OpenBSD, NetBSD, DragonFly BSD, Linux, MS-Windows 2000, MS-Windows XP and MS-Windows Vista support SMBus devices, but MS-Windows 98 and earlier versions do not.
[edit] See also
I2C (I2C)
Power Management Bus (PMBus)
Advanced Configuration and Power Interface (ACPI)
[edit] External links
SMBus website
SBS forum
SMBus at tech-faq.com
This article was originally based on material from the Free On-line Dictionary of Computing, which is licensed under the GFDL.
[edit] References
^ System Management Bus (SMBus) Specification Version 2.0
^ [www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf I2C-bus specification and user manual]
^ APPLICATION NOTE 476 Comparing the I?C Bus to the SMBus
^ Designing with SMBus 2.0
^ SMBus.org CRC-8 Calculator
^ CRC-8 for SMBus, PICBasic code
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